Design and implementation of a nibble-size multiplier for (-1+j)-base complex binary numbers

Tariq Jamil; Ahmad Al-Maashari; Amir Arshad Abdulghani

Design and implementation of a nibble-size multiplier for (-1+j)-base complex binary numbers

Tariq Jamil^*, Ahmad Al-Maashari, Amir Arshad Abdulghani

^*Corresponding author for this work

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

7 Citations (Scopus)

Abstract

Complex binary number system is unique, concise, one-unit notation for representing complex numbers in binary number system with base-(-l+j). With the procedure for arithmetic operations involving complex binary numbers already established, in this paper, we have presented design of a decoder-based minimum-delay multiplier circuit for nibble-sized complex binary numbers and implemented it on various Xilinx FPGAs.

Original language	English
Pages (from-to)	1539-1544
Number of pages	6
Journal	WSEAS Transactions on Circuits and Systems
Volume	4
Issue number	11
Publication status	Published - Nov 2005

Keywords

Arithmetic circuits
Complex binary number
Computer arithmetic
Decoder
FPGA
Multiplier

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

@article{04bac5292e914cc7b640562fa19a5488,

title = "Design and implementation of a nibble-size multiplier for (-1+j)-base complex binary numbers",

abstract = "Complex binary number system is unique, concise, one-unit notation for representing complex numbers in binary number system with base-(-l+j). With the procedure for arithmetic operations involving complex binary numbers already established, in this paper, we have presented design of a decoder-based minimum-delay multiplier circuit for nibble-sized complex binary numbers and implemented it on various Xilinx FPGAs.",

keywords = "Arithmetic circuits, Complex binary number, Computer arithmetic, Decoder, FPGA, Multiplier",

author = "Tariq Jamil and Ahmad Al-Maashari and Abdulghani, {Amir Arshad}",

year = "2005",

month = nov,

language = "English",

volume = "4",

pages = "1539--1544",

journal = "WSEAS Transactions on Circuits and Systems",

issn = "1109-2734",

publisher = "World Scientific and Engineering Academy and Society",

number = "11",

}

TY - JOUR

T1 - Design and implementation of a nibble-size multiplier for (-1+j)-base complex binary numbers

AU - Jamil, Tariq

AU - Al-Maashari, Ahmad

AU - Abdulghani, Amir Arshad

PY - 2005/11

Y1 - 2005/11

N2 - Complex binary number system is unique, concise, one-unit notation for representing complex numbers in binary number system with base-(-l+j). With the procedure for arithmetic operations involving complex binary numbers already established, in this paper, we have presented design of a decoder-based minimum-delay multiplier circuit for nibble-sized complex binary numbers and implemented it on various Xilinx FPGAs.

AB - Complex binary number system is unique, concise, one-unit notation for representing complex numbers in binary number system with base-(-l+j). With the procedure for arithmetic operations involving complex binary numbers already established, in this paper, we have presented design of a decoder-based minimum-delay multiplier circuit for nibble-sized complex binary numbers and implemented it on various Xilinx FPGAs.

KW - Arithmetic circuits

KW - Complex binary number

KW - Computer arithmetic

KW - Decoder

KW - FPGA

KW - Multiplier

UR - http://www.scopus.com/inward/record.url?scp=29944438787&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=29944438787&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:29944438787

SN - 1109-2734

VL - 4

SP - 1539

EP - 1544

JO - WSEAS Transactions on Circuits and Systems

JF - WSEAS Transactions on Circuits and Systems

IS - 11

ER -

Design and implementation of a nibble-size multiplier for (-1+j)-base complex binary numbers

Abstract

Keywords

ASJC Scopus subject areas

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