ملخص
Complex binary number system is unique, concise, one-unit notation for representing complex numbers in binary number system with base-(-l+j). With the procedure for arithmetic operations involving complex binary numbers already established, in this paper, we have presented design of a decoder-based minimum-delay multiplier circuit for nibble-sized complex binary numbers and implemented it on various Xilinx FPGAs.
اللغة الأصلية | English |
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الصفحات (من إلى) | 1539-1544 |
عدد الصفحات | 6 |
دورية | WSEAS Transactions on Circuits and Systems |
مستوى الصوت | 4 |
رقم الإصدار | 11 |
حالة النشر | Published - نوفمبر 2005 |
ASJC Scopus subject areas
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