Performance enhancement of multicore architecture

Medhat Awadalla*, Hanan Konsowa

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

3 Citations (Scopus)


Multicore processors integrate several cores on a single chip. The fixed architecture of multicore platforms often fails to accommodate the inherent diverse requirements of different applications. The permanent need to enhance the performance of multicore architecture motivates the development of a dynamic architecture. To address this issue, this paper presents new algorithms for thread selection in fetch stage. Moreover, this paper presents three new fetch stage policies, EACH-LOOP-FETCH, INC-FETCH, and WZ-FETCH, based on Ordinary Least Square (OLS) regression statistic method. These new fetch policies differ on thread selection time which is represented by instructions' count and window size. Furthermore, the simulation multicore tool, is adapted to cope with multicore processor dynamic design by adding a dynamic feature in the policy of thread selection in fetch stage. SPLASH2, parallel scientific workloads, has been used to validate the proposed adaptation for multi2sim. Intensive simulated experiments have been conducted and the obtained results show that remarkable performance enhancements have been achieved in terms of execution time and number of instructions per second. produces less broadcast operations compared to the typical algorithm.

Original languageEnglish
Pages (from-to)669-684
Number of pages16
JournalInternational Journal of Electrical and Computer Engineering
Issue number4
Publication statusPublished - Aug 1 2015
Externally publishedYes


  • Fetch policy
  • Multi2sim
  • Multicore
  • Ordinary Least Square (OLS)
  • Pipeline processor

ASJC Scopus subject areas

  • General Computer Science
  • Electrical and Electronic Engineering


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