Nibble-size Multiplier Circuit Designs and their FPGA Implementations for Complex Binary Number System

Tariq Jamil, Medhat Awadallah, Iftaquaruddin Mohammad

Research output: Contribution to journalArticlepeer-review


These days complex numbers are represented in computer arithmetic using a divide-and-conquer technique wherein the real part of the number is represented by a separate base-2 binary string and the imaginary part of the number is represented by a separate base-2 binary string. Then each binary string is treated separately to evaluate the result of any operation on the given complex number. Complex Binary Number System (CBNS) is (-1+j)-based binary number system which allows both real and imaginary components of the complex number to be collectively represented as single binary string. In this paper, we have presented two designs of nibble-size complex binary multiplier circuits (decoder-based, minimum-delay) and implemented them on various Xilinx FPGAs.
Original languageEnglish
Article numberIJEET_12_06_012
Pages (from-to)105-121
Number of pages17
JournalInternational Journal of Electrical Engineering and Technology
Issue number6
Publication statusPublished - Jun 2021


  • complex binary, complex number, decoder, multiplier, minimum delay

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