Hardware implementation and experiment validation of the VDDRHF color image filter

A. Boudabous; A. Ben Atitallah; L. Khriji; P. Kadionik; N. Masmoudi

doi:10.1109/SSD.2010.5585526

Hardware implementation and experiment validation of the VDDRHF color image filter

A. Boudabous^*, A. Ben Atitallah, L. Khriji, P. Kadionik, N. Masmoudi

^*Corresponding author for this work

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

This paper proposes a novel FPGA implementation of Vector Directional Distance Rational Hybrid Filter) (VDDRHF) for mixed noise suppression and fine-details preservation in color images. The Implementation was done, based on FPGA HW/SW validation using efficient hardware optimizations and non linear function approximations. The validation using FPGA board confirms the color image quality preservation. Our proposed architecture proves that HW/SW co-design present a high timing performance compared to software based solutions.

Original language	English
Title of host publication	2010 7th International Multi-Conference on Systems, Signals and Devices, SSD-10
DOIs	https://doi.org/10.1109/SSD.2010.5585526
Publication status	Published - 2010
Event	2010 7th International Multi-Conference on Systems, Signals and Devices, SSD-10 - Amman, Jordan Duration: Jun 27 2010 → Jun 29 2010

Publication series

Name	2010 7th International Multi-Conference on Systems, Signals and Devices, SSD-10

Other

Other	2010 7th International Multi-Conference on Systems, Signals and Devices, SSD-10
Country/Territory	Jordan
City	Amman
Period	6/27/10 → 6/29/10

Keywords

Architecture
Color image
FPGA implementation
Nios-II
VDDRHF filter
Validation

ASJC Scopus subject areas

Computer Networks and Communications
Signal Processing
Control and Systems Engineering

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10.1109/SSD.2010.5585526

Cite this

Boudabous, A., Ben Atitallah, A., Khriji, L., Kadionik, P., & Masmoudi, N. (2010). Hardware implementation and experiment validation of the VDDRHF color image filter. In 2010 7th International Multi-Conference on Systems, Signals and Devices, SSD-10 Article 5585526 (2010 7th International Multi-Conference on Systems, Signals and Devices, SSD-10). https://doi.org/10.1109/SSD.2010.5585526

Hardware implementation and experiment validation of the VDDRHF color image filter. / Boudabous, A.; Ben Atitallah, A.; Khriji, L. et al.
2010 7th International Multi-Conference on Systems, Signals and Devices, SSD-10. 2010. 5585526 (2010 7th International Multi-Conference on Systems, Signals and Devices, SSD-10).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Boudabous, A, Ben Atitallah, A, Khriji, L, Kadionik, P & Masmoudi, N 2010, Hardware implementation and experiment validation of the VDDRHF color image filter. in 2010 7th International Multi-Conference on Systems, Signals and Devices, SSD-10., 5585526, 2010 7th International Multi-Conference on Systems, Signals and Devices, SSD-10, 2010 7th International Multi-Conference on Systems, Signals and Devices, SSD-10, Amman, Jordan, 6/27/10. https://doi.org/10.1109/SSD.2010.5585526

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title = "Hardware implementation and experiment validation of the VDDRHF color image filter",

abstract = "This paper proposes a novel FPGA implementation of Vector Directional Distance Rational Hybrid Filter) (VDDRHF) for mixed noise suppression and fine-details preservation in color images. The Implementation was done, based on FPGA HW/SW validation using efficient hardware optimizations and non linear function approximations. The validation using FPGA board confirms the color image quality preservation. Our proposed architecture proves that HW/SW co-design present a high timing performance compared to software based solutions.",

keywords = "Architecture, Color image, FPGA implementation, Nios-II, VDDRHF filter, Validation",

author = "A. Boudabous and {Ben Atitallah}, A. and L. Khriji and P. Kadionik and N. Masmoudi",

year = "2010",

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AU - Masmoudi, N.

PY - 2010

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AB - This paper proposes a novel FPGA implementation of Vector Directional Distance Rational Hybrid Filter) (VDDRHF) for mixed noise suppression and fine-details preservation in color images. The Implementation was done, based on FPGA HW/SW validation using efficient hardware optimizations and non linear function approximations. The validation using FPGA board confirms the color image quality preservation. Our proposed architecture proves that HW/SW co-design present a high timing performance compared to software based solutions.

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SN - 9781424475346

T3 - 2010 7th International Multi-Conference on Systems, Signals and Devices, SSD-10

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ER -

Hardware implementation and experiment validation of the VDDRHF color image filter

Abstract

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Keywords

ASJC Scopus subject areas

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