An analytical comparison of the spidergon and rectangular mesh NoCs

Mahmoud Moadeli*, Ali Shahrabi, Wim Vanderbauwhede, Mohamed Ould-Khaoua

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review


Networks on chip (NoC) emerged as a structured and scalable communication medium for development of future Systems-on-Chip (SoC). Due to its unique features in terms of scalability and ease of synthesis, the (rectangular) mesh topology is regarded as an appropriate candidate for on-chip network development. On the other hand, the Spidergon NoC has been proposed as an alternative topology to realize cost effective multi-processor SoC (MPSoC) development. This paper presents analytical models of the average message latency and network throughput for both rectangular mesh and the Spidergon NoC employing wormhole switching. For each model, the validity of the analysis is verified by comparing the analytical model against the results produced by a discrete event simulator. Using the developed models, we then compare these topologies from different perspectives including manufacturing issues, message latency and network throughput.

Original languageEnglish
Pages (from-to)167-188
Number of pages22
JournalJournal of Interconnection Networks
Issue number1-2
Publication statusPublished - 2009


  • Network on-chip
  • Performance model
  • Rectangular mesh
  • Spidergon

ASJC Scopus subject areas

  • Computer Networks and Communications


Dive into the research topics of 'An analytical comparison of the spidergon and rectangular mesh NoCs'. Together they form a unique fingerprint.

Cite this