FPGA codesign implementation of vector directional filter

A. Boudabous*, A. Ben Atitallah, P. Kadionik, L. Khriji, N. Masmoudi

*المؤلف المقابل لهذا العمل

نتاج البحث: Conference contribution

3 اقتباسات (Scopus)

ملخص

Recently, Vector Directional Filter (VDF) have been developed either as software based applications or hardware using DSP (digital single processing) technologies. In this paper, we present a new efficient hardware/software (HW/SW) codesign implementation of the VDF using embedded system development board. By means of VHDL language, hardware accelerator including VDF algorithm is implemented with fast pipelined architecture. The remaining parts were realized in software using NIOS II softcore processor and Clinux as operating system. Experimental results confirm that the use of hardware accelerator gives good results concerning image quality and filtering speed.

اللغة الأصليةEnglish
عنوان منشور المضيف2008 1st International Workshops on Image Processing Theory, Tools and Applications, IPTA 2008
المعرِّفات الرقمية للأشياء
حالة النشرPublished - 2008
الحدث2008 1st International Workshops on Image Processing Theory, Tools and Applications, IPTA 2008 - Sousse, Tunisia
المدة: نوفمبر ٢٣ ٢٠٠٨نوفمبر ٢٦ ٢٠٠٨

سلسلة المنشورات

الاسم2008 1st International Workshops on Image Processing Theory, Tools and Applications, IPTA 2008

Other

Other2008 1st International Workshops on Image Processing Theory, Tools and Applications, IPTA 2008
الدولة/الإقليمTunisia
المدينةSousse
المدة١١/٢٣/٠٨١١/٢٦/٠٨

ASJC Scopus subject areas

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